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ISL54066
Data Sheet February 25, 2009 FN6584.0
+1.8V to +6.5V, High Off-Isolation, Dual SPST Analog Switch with Negative Signal Capability
The Intersil ISL54066 device is a low ON-resistance, high off-isolation, low voltage, dual single-pole/single-throw (SPST) analog switch. It was designed to operate from a single +1.8V to +6.5V supply and can pass signals that swing 6.5V below the positive supply rail. Targeted applications include battery powered equipment that benefit from low rON (1), high off-isolation (80dB) and fast switching speeds (tON = 40ns, tOFF = 30ns). The digital logic input is 1.8V logic-compatible when using a single +3V supply. The ISL54066 incorporates a T-switch architecture. This approach results in excellent signal off-isolation while retaining a low impedance signal path when switches are ON. The ISL54066 is offered in small form factor packages, alleviating board space limitations. The ISL54066 is available in 10Ld TQFN and TDFN packages. The ISL54066 is a dual single-pole/single-throw (SPST) normally open (NO) switch with independent logic control.
TABLE 1. FEATURES AT A GLANCE ISL54066 Number of Switches Switch Type 4.3V rON 4.3V tON/tOFF 2.7V rON 2.7V tON/tOFF 1.8V rON 1.8V tON/tOFF Packages 2 SPST NO 1 40ns/30ns 1.5 60ns/30ns 3 180ns/44ns 10 Ld TQFN, 10 Ld TDFN
Features
* Pb-free (RoHS Compliant) * Negative Signal Capability * T-switch Architecture * ON-Resistance (rON) - V+ = +4.5V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 - V+ = +4.3V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 - V+ = +2.7V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 - V+ = +1.8V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 * rON Matching Between Channels . . . . . . . . . . . . . . . . . 10m * rON Flatness Across Signal Range . . . . . . . . . . . . . . . . . 0.2 * Single Supply Operation . . . . . . . . . . . . . . . . .+1.8V to +6.5V * Low Power Consumption (PD). . . . . . . . . . . . . . . . . . 30nA * Fast Switching Action (V+ = +4.3V) - tON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40ns - tOFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30ns * ESD HBM Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>6kV * 1.8V Logic Compatible (+3V Supply) * Low I+ Current when VinH is not at the V+ Rail * Available in 10 Ld TQFN and 10 Ld 3x3 TDFN
Applications
* Battery powered, Handheld, and Portable Equipment - Cellular/mobile Phones - Pagers - Laptops, Notebooks, Palmtops * Portable Test and Measurement * Medical Equipment * Audio and Video Switching
Related Literature
* Technical Brief TB363 "Guidelines for Handling and Processing Moisture Sensitive Surface Mount Devices (SMDs)" * Application Note AN557 "Recommended Test Procedures for Analog Switches"
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2009. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
ISL54066 Pinouts
(Note 1) ISL54066 (10 LD TDFN) TOP VIEW
CTL1 1 OUT1 2 GND1 3 IN1 4 10k GND3 5 10k 10 CTL2 9 OUT2
Truth Table
CTLx 0 1
200k 200k
INx/OUTx OPEN CLOSED
NOTE:
Logic "0" 0.5V. Logic "1" 1.4V with a 3V supply.
Pin Descriptions
8 GND2
PIN
7 IN2 6 V+
FUNCTION System Power Supply Input (+1.8V to +6.5V) 10k Input Shunt Ground 200k Output Shunt Ground IC Ground Connection Digital Control Input Switch x Input Switch x Output
V+ GND1 GND2
ISL54066 (10 LD TQFN) TOP VIEW
CTL1 7 OUT1 8 200k GND1 9 10k 200k IN1 10 1 GND3 2 V+ 10k 4 CTL2
GND3 CTLx INx OUTx
6 5 OUT2
GND2
3
IN2
NOTE: 1. Switches Shown for CTLx = Logic "0". Logic "0" 0.5V. Logic "1" 1.4V with a 3V supply.
Ordering Information
PART NUMBER ISL54066IRZ (Note 3) ISL54066IRZ-T (Notes 2, 3) ISL54066IRUZ-T (Notes 2, 4) NOTES: 2. Please refer to TB347 for details on reel specifications. 3. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD020. 4. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. PART MARKING 4066 4066 9 TEMP. RANGE (C) -40 to +85 -40 to +85 -40 to +85 PACKAGE (Pb-free) 10 Ld 3x3 TDFN 10 Ld 3x3 TDFN (Tape and Reel) 10 Ld TQFN (Tape and Reel) PKG. DWG. # L10.3x3A L10.3x3A L10.1.8x1.4A
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ISL54066
Absolute Maximum Ratings
V+ to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 7.0V Input Voltages INx (Note 5) . . . . . . . . . . . . . . . . . . . . . . . (V+ - 7V) to ((V+) + 0.5V) CNTLx (Note 5) . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to ((V+) + 0.5V) Output Voltages OUTx (Note 5) . . . . . . . . . . . . . . . . . . . . . (V+ - 7V) to ((V+) + 0.5V) Continuous Current INx or OUTx. . . . . . . . . . . . . . . . . . . . . 300mA Peak Current INx or OUTx (Pulsed 1ms, 10% Duty Cycle, Max) . . . . . . . . . . . . . . . . . . 500mA ESD Rating: Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>6kV Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>400V Charged Device Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . >1.5kV
Thermal Information
Thermal Resistance (Typical) JA (C/W) JC (C/W) 10 Ld 3x3 TDFN Package (Notes 6, 8) 55 18 10 Ld TQFN Package (Note 7) . . . . . 155 N/A Maximum Junction Temperature (Plastic Package). . . . . . . +150C Maximum Storage Temperature Range . . . . . . . . . . . -65C to +150C Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp)
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -40C to +85C Power Supply Range . . . . . . . . . . . . . . . . . . . . . . . . +1.8V to +6.5V Analog Signal Range . . . . . . . . . . . . . . . . . . . . . . . (V+ - 6.5)V to V+
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty.
NOTES: 5. Signals on NC, NO, IN, or COM exceeding V+ or GND by specified amount are clamped by internal diodes. Limit forward diode current to maximum current ratings. 6. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with "direct attach" features. See Tech Brief TB379. 7. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 8. For JC, the "case temp" location is the center of the exposed metal pad on the package underside.
Electrical Specifications - 5V Supply
Test Conditions: V+ = +4.5V to +5.5V, GND = 0V, VCTL_H = 2.4V, VCTL_L = 0.8V (Note 9), Unless Otherwise Specified. TEST CONDITIONS TEMP MIN (C) (Notes 10, 11) TYP MAX (Notes 10, 11) UNITS m m
PARAMETER ANALOG SWITCH CHARACTERISTICS ON-Resistance, rON rON Matching Between Channels, rON rON Flatness, RFLAT(ON) DYNAMIC CHARACTERISTICS Turn-ON Time, tON Turn-OFF Time, tOFF Charge Injection, Q OFF-Isolation Crosstalk (Channel-to-Channel) Total Harmonic Distortion -3dB Bandwidth INx OFF Capacitance, COFF OUTx ON Capacitance, COUT(ON) Positive Supply Current, I+
V+ = 4.5V, IOUT = 100mA, VIN = (V+ - 6.5) to V+, (See Figure 4) V+ = 4.5V, IOUT = 100mA, VIN = Voltage at max rON, (Note 13) V+ = 4.5V, IOUT = 100mA, VIN = (V+ - 6.5) to V+, (Note 12)
25 Full 25 Full 25 Full
-
1 1.2 5 10 0.21 0.27
-
V+ = 4.5V, VIN = 3.0V, RL = 50, CL = 35pF (See Figure 1) V+ = 4.5V, VIN = 3.0V, RL = 50, CL = 35pF (See Figure 1) VG = 0V, RG = 0, CL = 1.0nF (See Figure 2) RL = 50, CL = 5pF, f = 1MHz, VINx = 1VRMS (See Figure 3) RL = 50, CL = 5pF, f = 1MHz, VIN1 = 1VRMS (See Figure 5) f = 20Hz to 20kHz, VOUT = 2VP-P, RL = 32 RL = 50 f = 1MHz, GND1 = float (See Figure 6) f = 1MHz, GND2 = float (See Figure 6)
25 Full 25 Full 25 25 25 25 25 25 25
-
39 46 27 33 170 70 -80 0.015 30 33 124
-
ns ns ns ns pC dB dB % MHz pF pF
POWER SUPPLY CHARACTERISTICS V+ = +5.5V, VCTLx = 0V or V+ 25 Full 0.03 1.64 0.1 A A
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ISL54066
Electrical Specifications - 5V Supply
Test Conditions: V+ = +4.5V to +5.5V, GND = 0V, VCTL_H = 2.4V, VCTL_L = 0.8V (Note 9), Unless Otherwise Specified. (Continued) TEST CONDITIONS TEMP MIN (C) (Notes 10, 11) TYP MAX (Notes 10, 11) UNITS
PARAMETER DIGITAL INPUT CHARACTERISTICS Input Voltage Low, VCTLx_L Input Voltage High, VCTLx_H Input Current, ICTLx_H, ICTLx_L
Full Full V+ = 5.5V, VCTLx = 0V or V+ 25 Full
2.4 -0.1 -
0.9
0.8 0.1 -
V V A A
Electrical Specifications - 4.3V Supply Test Conditions: V+ = +3.9V to +4.5V, GND = 0V, VCTL_H = 1.6V, VCTL_L = 0.5V (Note 9),
Unless Otherwise Specified. TEST CONDITIONS TEMP MIN MAX (C) (Notes 10, 11) TYP (Notes 10, 11) UNITS
PARAMETER ANALOG SWITCH CHARACTERISTICS ON-Resistance, rON
V+ = 4.3V, IOUT = 100mA, VIN = (V+ - 6.5) to V+, (See Figure 4) V+ = 4.3V, IOUT = 100mA, VIN = Voltage at max rON, (Note 13) V+ = 4.3V, IOUT = 100mA, VIN = (V+ - 6.5) to V+ (Note 12, 14)
25 Full 25 Full 25 Full
-
1 1.2 5 10 0.2 0.27
-
m m
rON Matching Between Channels, rON rON Flatness, RFLAT(ON)
DYNAMIC CHARACTERISTICS Turn-ON Time, tON V+ = 3.9V, VIN = 3.0V, RL = 50, CL = 35pF (See Figure 1) V+ = 3.9V, VIN = 3.0V, RL = 50, CL = 35pF, (See Figure 1) CL = 1.0nF, VG = 0V, RG = 0, (See Figure 2) RL = 50, CL = 5pF, f = 1MHz, VINx = 1VRMS (See Figure 3) RL = 50, CL = 5pF, f = 1MHz, VIN1 = 1VRMS (See Figure 5) f = 20Hz to 20kHz, VCOM = 2VP-P, RL = 32 f = 1MHz, GND1 = float (See Figure 6) f = 1MHz, GND2 = float (See Figure 6) 25 Full 25 Full 25 25 25 25 25 25 40 47 31 34 200 70 -80 0.02 33 124 ns ns ns ns pC dB dB % pF pF
Turn-OFF Time, tOFF
Charge Injection, Q OFF-Isolation Crosstalk (Channel-to-Channel) Total Harmonic Distortion INx OFF Capacitance, COFF OUTx ON Capacitance, COUT(ON)
POWER SUPPLY CHARACTERISTICS Positive Supply Current, I+ V+ = +4.5V, VCTLx = 0V or V+ 25 Full Positive Supply Current, I+ V+ = +4.2V, VCTL1 = VCTL2 = 2.85V 25 0.02 1.76 0.95 0.1 12 A A A
DIGITAL INPUT CHARACTERISTICS Input Voltage Low, VCTLx_L Input Voltage High, VCTLx_H Input Current, ICTLx_H, ICTLx_L V+ = 4.5V, VCTLx = 0V or V+ Full Full 25 Full 1.6 -0.5 0.63 0.5 0.5 V V A A
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ISL54066
Electrical Specifications - 3V Supply
Test Conditions: V+ = +2.7V to +3.3V, GND = 0V, VCTL_H = 1.4V, VCTL_L = 0.5V (Note 9), Unless Otherwise Specified. TEST CONDITIONS TEMP MIN MAX (C) (Notes 10, 11) TYP (Notes 10, 11) UNITS
PARAMETER ANALOG SWITCH CHARACTERISTICS ON-Resistance, rON
V+ = 2.7V, IOUT = 100mA, VIN = (V+ - 6.5) to V+ (See Figure 4) V+ = 2.7V, IOUT = 100mA, VIN = Voltage at max rON, (Note 13) V+ = 2.7V, IOUT = 100mA, VIN = (V+ - 6.5) to V+ (Notes 12, 14)
25 Full 25 Full 25 Full
-
1.5 1.9 10 10 0.63 0.68
1 1.35
m m
rON Matching Between Channels, rON rON Flatness, RFLAT(ON)
DYNAMIC CHARACTERISTICS Turn-ON Time, tON V+ = 2.7V, VIN = 1.5V, RL = 50, CL = 35pF (See Figure 1) V+ = 2.7V, VIN = 1.5V, RL = 50, CL = 35pF (See Figure 1) CL = 1.0nF, VG = 0V, RG = 0, (See Figure 2) RL = 50, CL = 5pF, f = 1MHz, VINx = 1VRMS (See Figure 3) RL = 50, CL = 5pF, f = 1MHz, VIN1 = 1VRMS (See Figure 5) f = 20Hz to 20kHz, VOUT = 2VP-P, RL = 32 f = 1MHz, GND1 = float (See Figure 6) f = 1MHz, GND2 = float (See Figure 6) 25 Full 25 Full 25 25 25 25 25 25 60 68 31 35 150 70 -80 0.04 33 124 ns ns ns ns pC dB dB % pF pF
Turn-OFF Time, tOFF
Charge Injection, Q OFF-Isolation Crosstalk (Channel-to-Channel) Total Harmonic Distortion INx OFF Capacitance, COFF OUTx ON Capacitance, COUT(ON)
POWER SUPPLY CHARACTERISTICS Positive Supply Current, I+ V+ = +3.6V, VCTLx = 0V or V+ 25 Full DIGITAL INPUT CHARACTERISTICS Input Voltage Low, VCTLx_L Input Voltage High, VCTLx_H Input Current, ICTLx_H, ICTLx_L V+ = 3.3V, VCTL x = 0V or V+ 25 25 25 Full 1.4 -0.5 0.55 0.5 0.5 V V A A 0.02 1.76 A A
Electrical Specifications - 1.8V Supply Test Conditions: V+ = +1.8V, GND = 0V, VCTL_H = 1.0V, VCTL_L = 0.4V (Note 9),
Unless Otherwise Specified. PARAMETER ANALOG SWITCH CHARACTERISTICS ON-Resistance, rON V+ = 1.8V, IOUT = 100mA, VIN = (V+ - 6.5V) to V+, (See Figure 4) V+ = 1.8V, IOUT = 100mA, VIN = Voltage at max rON, (Note 13) V+ = 1.8V, IOUT = 100mA, VIN = (V+ - 6.5) to V+, (Note 12) 25 Full 25 Full 25 Full 3 3.2 20 20 2.3 2.5 m m TEST CONDITIONS TEMP MIN MAX (C) (Notes 10, 11) TYP (Notes 10, 11) UNITS
rON Matching Between Channels, RON rON Flatness, RFLAT(ON)
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ISL54066
Electrical Specifications - 1.8V Supply Test Conditions: V+ = +1.8V, GND = 0V, VCTL_H = 1.0V, VCTL_L = 0.4V (Note 9),
Unless Otherwise Specified. (Continued) PARAMETER DYNAMIC CHARACTERISTICS Turn-ON Time, tON Turn-OFF Time, tOFF Charge Injection, Q -3dB Bandwidth INx OFF Capacitance, COFF OUTx ON Capacitance, COUT(ON) V+ = 1.8V, VIN = 1.8V, RL = 50, CL = 35pF (See Figure 1) V+ = 1.8V, VIN = 1.8V, RL = 50, CL = 35pF (See Figure 1) CL = 1.0nF, VG = 0V, RG = 0, (See Figure 2) VCOM = 1VRMS, RL = 50, CL = 5pF f = 1MHz, GND1 = float (See Figure 6) f = 1MHz, GND2 = float (See Figure 6) 25 25 25 25 25 25 180 44 40 30 33 124 ns ns pC MHz pF pF TEST CONDITIONS TEMP MIN MAX (C) (Notes 10, 11) TYP (Notes 10, 11) UNITS
DIGITAL INPUT CHARACTERISTICS Input Voltage Low, VCTLx_L Input Voltage High, VCTLx_H Input Current, ICTLx_H, ICTLx_L V+ = 2.0V, VCTLx = 0V or V+ 25 25 25 Full NOTES: 9. VCTL_x = input voltage to perform proper function. 10. The algebraic convention, whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. 11. Parameters with MIN and/or MAX limits are 100% tested at +25C, unless otherwise specified. Temperature limits established by characterization and are not production tested. 12. Flatness is defined as the difference between maximum and minimum value of ON-resistance over the specified analog signal range. 13. rON matching between channels is calculated by subtracting the channel with the highest max rON value from the channel with lowest max rON value, between IN1 and IN2. 14. Limits established by characterization and are not production tested. 1.0 -0.5 0.5 0.4 V V A A
Test Circuits and Waveforms
V+ V+ LOGIC INPUT 50% 0V tOFF SWITCH INPUT VIN 90% SWITCH OUTPUT 0V tON VOUT 90% tr < 5ns tf < 5ns SWITCH INPUT IN CTL LOGIC INPUT GNDx RL 50 CL 35pF OUT VOUT C
Repeat test for all switches. CL includes fixture and stray capacitance. RL ----------------------V OUT = V (IN) R + r L ON FIGURE 1A. MEASUREMENT POINTS FIGURE 1. SWITCHING TIMES FIGURE 1B. TEST CIRCUIT
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FN6584.0 February 25, 2009
ISL54066 Test Circuits and Waveforms (Continued)
V+ C
RG SWITCH OUTPUT VOUT
INx
OUTx
VOUT
VOUT VG V+ ON OFF 0V Q = VOUT x CL GNDx CTLx CL
LOGIC INPUT
ON
LOGIC INPUT
Repeat test for all switches. FIGURE 2A. MEASUREMENT POINTS FIGURE 2. CHARGE INJECTION
V+ C *50 SOURCE SIGNAL GENERATOR V+ C INx rON = V1/100mA INx 0V VIN 100mA ANALYZER RL OUTx GNDx OUTx GNDx V1 CTLx V+
FIGURE 2B. TEST CIRCUIT
CTLx
Repeat test for all switches. FIGURE 3. OFF-ISOLATION TEST CIRCUIT FIGURE 4. rON TEST CIRCUIT
V+ C V+ C *50 SOURCE SIGNAL GENERATOR OUTx 0V OR V+
IN1
OUT1
50 IMPEDANCE ANALYZER
CTLx
CTL1 V+ INx OUT2 RL GNDx GND3
ANALYZER
IN2 *FLOAT GND1 and GND2
FIGURE 5. CROSSTALK TEST CIRCUIT
FIGURE 6. CAPACITANCE TEST CIRCUIT
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FN6584.0 February 25, 2009
ISL54066
Detailed Description
The ISL54066 is a dual single pole-single throw (SPST) analog switch that offers precise switching from a single 1.8V to 6.5V supply with low ON-resistance (1.5), high off-isolation, high speed operation (tON = 60ns, tOFF = 30ns) and negative signal swing capability. The device is especially well suited for portable battery powered equipment due to its low operating supply voltage (1.8V), low power consumption (30nA), and a tiny 1.8mmx1.4mm TQFN package or a 3mmx3mm TDFN package. The low rON resistance and rON flatness provide very low insertion loss and signal distortion for applications that require signal switching with minimal interference by the switch. In additon, the ISL54066 uses a T-switch architecture to achieve superior off-isolation from the input to output of the switch. (see Figure 8). To prevent forward biasing these diodes, V+ must be applied before any input signals, and the input signal voltages must remain between (V+ - 6.5V) and V+. If these conditions cannot be guaranteed, then precautions must be implemented to prohibit the current and voltage at the logic pin and signal pins from exceeding the maximum ratings of the switch. The following two methods can be used to provided additional protection to limit the current in the event that the voltage at a logic pin or switch terminal goes above the V+ rail. Logic inputs can be protected by adding a 1k resistor in series with the logic input (see Figure 8). The resistor limits the input current below the threshold that produces permanent damage. This method is not acceptable for the signal path inputs. Adding a series resistor to the switch input defeats the purpose of using a low rON switch. Alternatively, connecting external Schottky diodes from the V+ rail to the signal pins will shunt the fault current through the Schottky diode instead of through the internal ESD diodes, thereby protecting the switch. These Schottky diodes must be sized to handle the expected fault current..
V+ +RING
Input/Output Shunt Resistors
The ISL54066 contains input and output shunts resistors on the switch terminals. On the INx pins, there are 10k shunts to the GND1 pin. On the OUTx pins, there are 200k shunts to the GND2 pin. The input shunts are designed to discharge voltage that may be built up on the input pins, such as DC offsets due to AC-coupled signals. The output shunts are designed to bleed off any charge that may accumulate on the output pins when the switch is turned off. To have the shunt resistors enabled, connect the GND1 and GND2 pins to GND3. The GND3 pin is the main ground of the ISL54066 IC. The shunt resistors can be disconnected from the IC by floating the appropriate GND1 and GND2 pin.
VINx
VOUTx
Grounding Considerations
For maximum off-isolation performance, it is recommended to follow a star ground configuration of the GNDx pins (see Figure 7). Grounding the GND1, GND2 and GND3 pins to a star ground ensures there are no cross conduction of ground currents between the ground pins, which effect the off-isolation capability of the switch.
V+ 1k
CLAMP
LOGIC INPUTS
GND -RING
FIGURE 8. OVERVOLTAGE PROTECTION
VDD IN1 ISL54066 IN2 CTL1 CTL2 GND3 OUT2 GND1 GND2 OUT1 0.1F
Power-Supply Considerations
The ISL54066 construction is typical of most single supply CMOS analog switches which have two supply pins: V+ and GND. V+ and GND provide the CMOS switch bias and sets their analog voltage limits. Unlike switches with a 5.5V maximum supply voltage, the ISL54066 have a 6.5V maximum supply voltage providing plenty of head room for the 10% tolerance of 5.5V supplies due to overshoot and noise spikes. The minimum recommended supply voltage is +1.8V. It is important to note that the input signal range, switching times, and on-resistance degrade at lower supply voltages. Refer to the "Electrical Specifications" tables, beginning on page 3 and "Typical Performance Curves", beginning on page 10 for details.
FIGURE 7. STAR GROUNDING CONFIGURATION
Supply Sequencing and Overvoltage Protection
With any CMOS device, proper power supply sequencing is required to protect the device from excessive input currents which might permanently damage the IC. All I/O pins contain ESD protection diodes from the pin to V+ and to GND 8
FN6584.0 February 25, 2009
ISL54066
V+ and GND also power the internal logic and level shifters. The level shifters convert the input logic levels to V+ and GND signals levels to drive the analog switch gate terminals. A high frequency decoupling capacitor placed as close to the V+ and GND pin as possible is recommended for proper operation of the switch. A value of 0.1F is highly recommended.
High-Frequency Performance
In 50 systems, the ISL54066 has a -3dB bandwidth of 30MHz (see Figure 19). The frequency response is very consistent over a wide V+ range and for varying analog signal levels. An OFF switch acts like a capacitor and passes higher frequencies with less attenuation, resulting in signal feedthrough from a switch's input to its output. Off-Isolation is the resistance to this feed-through, while Crosstalk indicates the amount of feedthrough from one switch to another. Figure 20 details the high Off-Isolation and Crosstalk rejection provided by this part. At 1MHz, Off-Isolation is approximately 70dB in 50 systems, decreasing approximately 40dB per decade as frequency increases. Crosstalk is approximately -80dB at 1MHz in 50 systems.
Negative Signal Capability
The ISL54066 contains circuitry that allows the analog input signal to swing below ground. The device has an analog signal range of 6.5V below V+ up to the V+ rail (see Figure 14) while maintaining low rON performance. For example, if V+ = 5V, then the analog input signal range is from -1.5V to +5V. If V+ = 2.7V then the range is from -3.8V to +2.7V.
Logic-Level Thresholds
This switch family is 1.8V CMOS compatible (0.45V VOLMAX and 1.35V VOHMIN) over a supply range of 1.8V to 3.3V (see Figure 16). At 3.3V the VIL level is 0.5V maximum. This is still below the 1.8V CMOS guaranteed low output maximum level of 0.45V, but noise margin is reduced. At 3.3V the VIH level is 1.4V minimum. While this is above the 1.8V CMOS guaranteed high output minimum of 1.35V under most operating conditions the switch will recognize this as a valid logic high. The digital input stages draw supply current whenever the digital input voltage is not at one of the supply rails. Driving the digital input signals from GND to V+ with a fast transition time minimizes power dissipation. The ISL54066 has been designed to minimize the supply current whenever the digital input voltage is not driven to the supply rails (0V to V+). For example, driving the device with 2.85V logic high while operating with a 4.2V supply, the device draws only 1A of current.
Leakage Considerations
Reverse ESD protection diodes are internally connected between each analog-signal pin, V+ and GND. One of these diodes conducts if any analog signal exceeds the recommended analog signal range. Virtually all the analog switch leakage current comes from the ESD diodes and reversed biased junctions in the switch cell. Although the ESD diodes on a given signal pin are identical and therefore fairly well balanced, they are reverse biased differently. Each is biased to either the +Ring or -Ring and the analog input signal. This means their leakages will vary as the signal varies. The difference in the two diode leakages to the +Ring or -Ring and the reverse biased junctions at the internal switch cell constitutes the analog-signal-path leakage current.
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FN6584.0 February 25, 2009
ISL54066 Typical Performance Curves TA = +25C, Unless Otherwise Specified
2.6 2.4 2.2 2.0 rON () 1.8 1.6 1.4 1.2 1.0 0.8 -6 V+ = 2.7V 0.7 V+ = 4.5V 0.6 0.5 -5 -4 -3 -2 -1 0 1 2 3 4 5 0.4 -3 -2 -1 0 1 VOUT (V) 2 3 4 5 T = -40C rON () ICOM = 100mA V+ = 1.8V 1.4 1.3 1.2 1.1 1.0 0.9 0.8 T = +25C T = +85C V+ = 4.5V IOUT = 100mA
VCOM (V)
FIGURE 9. ON-RESISTANCE vs SUPPLY VOLTAGE vs SWITCH VOLTAGE
1.4 V+ = 4.3V 1.3 1.2 1.1 1.0 rON () 0.9 0.8 0.7 0.6 0.5 0.4 -3 -2 -1 0 1 VOUT (V) 2 3 4 5 T = -40C T = +25C T = +85C IOUT = 100mA
FIGURE 10. ON-RESISTANCE vs SWITCH VOLTAGE
2.0 1.9 1.8 1.7 1.6 1.5 rON () 1.4 1.3 1.2 1.1 1.0 0.9 0.8 0.7 0.6 -5 -4 -3 -2 -1 0 VOUT (V) 1 2 3 4 T = +25C T = -40C T = +85C V+ = 2.7V IOUT = 100mA
FIGURE 11. ON-RESISTANCE vs SWITCH VOLTAGE
4.0 3.5 3.0 2.5 rON () 2.0 1.5 T = 85C 1.0 0.5 0.0 -6 T = 25C V+ = 1.8V IOUT = 100mA ANALOG SIGNAL RANGE (V)
FIGURE 12. ON-RESISTANCE vs SWITCH VOLTAGE
6 5 4 3 2 1 0 -1 -2 -3 -4 -5 SIGNAL MIN SIGNAL MAX
T = -40C
-5 -4 -3 -2 -1 VOUT (V) 0 1 2 3
-6 1.5
2.0
2.5
3.0 3.5 4.0 4.5 SUPPLY VOLTAGE (V)
5.0
5.5
6.0
FIGURE 13. ON-RESISTANCE vs SWITCH VOLTAGE
FIGURE 14. ANALOG SIGNAL RANGE vs SUPPLY VOLTAGE
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FN6584.0 February 25, 2009
ISL54066 Typical Performance Curves TA = +25C, Unless Otherwise Specified (Continued)
700 650 600 550 500 450 Q (pC) 400 350 300 250 200 150 100 50 0 -5 -4 -3 -2 -1 0 1 VCOM (V) 2 3 4 5 6 V+ = 2.0V V+ = 3.3V VCTL_H AND VCTL_L V+ = 4.5V ABSOLUTE VALUES V+ = 5.5V 1.6 1.5 1.4 1.3 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 1.5 2.0 2.5 3.0 V+ (V) 3.5 4.0 4.5 VCTL_L VCTL_H
FIGURE 15. CHARGE INJECTION vs SWITCH VOLTAGE
160 T = -40C 140 120 100 T = +25C T = +85C
FIGURE 16. DIGITAL SWITCHING POINT vs SUPPLY VOLTAGE
40 T = -40C 35 30 25 tOFF (ns) 20 15 10 5 0 T = +25C T = +85C
tON (ns)
80 60 40 20 0
1.8
3.3 V+ (V)
4.5
5.5
1.8
3.3 V+ (V)
4.5
5.5
FIGURE 17. TURN-ON TIME vs SUPPLY VOLTAGE
1 V+ = 1.8V to 5.5V 0 -1 NORMALIZED GAIN (dB) CROSSTALK (dB) -2 -3 -4 -5 -6 -7 -8 1k RL = 50 VIN = 1VRMS @ 0VDC OFFSET
FIGURE 18. TURN-OFF TIME vs SUPPLY VOLTAGE
20 10 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 OFF-ISOLATION CROSSTALK V+ = 1.8V to 5.5V RL = 50 VIN = 1VRMS @ 0VDC OFFSET
10k
100k 1M 10M FREQUENCY (Hz)
100M
1G
-120 1k
10k
100k 1M 10M FREQUENCY (Hz)
100M
1G
FIGURE 19. FREQUENCY RESPONSE
FIGURE 20. CROSSTALK AND OFF-ISOLATION
11
FN6584.0 February 25, 2009
ISL54066 Typical Performance Curves TA = +25C, Unless Otherwise Specified (Continued) 0.09 Die Characteristics
0.08 0.07 360mVRMS 0.06 THD+N (%) 0.05 0.04 0.03 0.02 0.01 0 20 V+ = 3.3V VBIAS = 0VDC RL = 32 100 200 1k 2k FREQUENCY (Hz) 10k 20k 177mVRMS 707mVRMS
SUBSTRATE POTENTIAL (POWERED UP): GND (DFN Paddle Connection: Tie to GND or Float) TRANSISTOR COUNT: 432 PROCESS: Submicron CMOS
FIGURE 21. TOTAL HARMONIC DISTORTION vs FREQUENCY
12
FN6584.0 February 25, 2009
ISL54066 Ultra Thin Quad Flat No-Lead Plastic Package (UTQFN)
D A B
L10.1.8x1.4A
10 LEAD ULTRA THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE MILLIMETERS SYMBOL MIN 0.45 NOMINAL 0.50 0.127 REF 0.15 1.75 1.35 0.20 1.80 1.40 0.40 BSC 0.35 0.45 0.40 0.50 10 2 3 0 12 0.45 0.55 0.25 1.85 1.45 MAX 0.55 0.05 NOTES 5 2 3 3 4 Rev. 3 6/06 NOTES: 1. Dimensioning and tolerancing conform to ASME Y14.5-1994. 2. N is the number of terminals. 3. Nd and Ne refer to the number of terminals on D and E side, respectively. 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. Maximum package warpage is 0.05mm. 8. Maximum allowable burrs is 0.076mm in all directions.
6 INDEX AREA 2X 2X 0.10 C
N
E
1 0.10 C
2
A A1
TOP VIEW
A3 b
0.10 C 0.05 C SEATING PLANE A1 SIDE VIEW A
D
C
E e L L1 N
(DATUM A) PIN #1 ID L1 NX L 1 2 NX b 5 10X 0.10 M C A B 0.05 M C 5 7 e BOTTOM VIEW (DATUM B)
Nd Ne
NX (b) 5
(A1)
C L
L SECTION "C-C" CC 2.20 1.00 0.60 e TERMINAL TIP
9. JEDEC Reference MO-255. 10. For additional information, to assist with the PCB Land Pattern Design effort, see Intersil Technical Brief TB389.
1.00
0.50 1.80 0.40 0.20 0.40 10 LAND PATTERN 0.20
13
FN6584.0 February 25, 2009
ISL54066 Thin Dual Flat No-Lead Plastic Package (TDFN)
2X 0.10 C A A D 2X 0.10 C B
L10.3x3A
10 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE MILLIMETERS SYMBOL A A1
E
MIN 0.70 -
NOMINAL 0.75 0.20 REF
MAX 0.80 0.05
NOTES -
6 INDEX AREA TOP VIEW B
A3 b D D2 E
// A 0.10 C 0.08 C
0.20 2.95 2.25 2.95 1.45
0.25 3.0 2.30 3.0 1.50 0.50 BSC
0.30 3.05 2.35 3.05 1.55
5, 8 7, 8 7, 8 -
E2 e k
0.25 0.25
0.30 10 5
0.35
8 2 3 Rev. 3 3/06
C SEATING PLANE
SIDE VIEW
A3
L N
D2 (DATUM B) 1 2 D2/2
7
8
Nd NOTES:
6 INDEX AREA (DATUM A)
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
NX k E2 E2/2
2. N is the number of terminals. 3. Nd refers to the number of terminals on D. 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature.
NX L N 8 N-1 NX b e (Nd-1)Xe REF. BOTTOM VIEW C L NX (b) 5 SECTION "C-C" CC e TERMINAL TIP (A1) L1 9L 5 0.10 M C A B
7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. 8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389. 9. Compliant to JEDEC MO-229-WEED-3 except for D2 dimensions.
FOR ODD TERMINAL/SIDE
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 14
FN6584.0 February 25, 2009

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